User Tools

Site Tools


MOS Capacitor & MOSFET in 2D Tutorial

Author: Daryoush Nosraty Alamdary, nextnano GmbH


Part 1: Capacitance-voltage characteristics of a 2D MOS capacitor

In the first part of this tutorial we discuss the capacitance-voltage (C-V) characteristics of the MOS capacitor in a 2D simulation. (For a 1D simulation of the C-V characteristics, see also this tutorial: Capacitance-Voltage curve of a "metal"-insulator-semiconductor (MIS) structure). Our MOS has the same dimensions and properties (channel length, doping profiles and gate contact type) as the corresponding MOSFET discussed in Part 2.

Part 2: Current-voltage characteristics of a 2D n-Channel MOSFET

In the second part of the tutorial, we start with the design of the MOSFET based on its 2D MOS capacitor, and then discuss its input and output characteristics and their respective conductances, namely transconductance and channel conductance.

Part 3: Mobility models and pinch-off in a 2D n-Channel MOSFET

In this part we discuss and compare the effect of different mobility models on the output characteristics of the MOSFET and how they affect properties such as pinch-off, saturation, etc.

The purpose of this tutorial is to show how the results of our simulation software (which solves the Poisson and drift-diffusion current equations numerically) compare with analytical equations given in standard text books on MOSFETs. The analytical equations use certain approximations and assumptions which limit their applicability. Nevertheless, in most cases the agreement is very good as demonstrated in this tutorial.


  1. [Goetzberger] A. Goetzberger, M. Schulz, Fundamentals of MOS Technology, In: H. J. Queisser (eds) Festkörperprobleme 13, Advances in Solid State Physics 13, Springer, Berlin, Heidelberg, 309-336 (1973),
  2. [Wu] Y.-C. Wu, Y.-R. Jhan, 3D TCAD Simulation for CMOS Nanoeletronic Devices, Springer, Singapore (2018)
  3. [Sze] S. M. Sze, K. K. NG, Physics of Semiconductor Devices (3rd ed.), John Wiley, New York (2007)
  4. [Brews] J. R. Brews, W. Fichtner, E. H. Nicollian, S. M. Sze, Generalized guide for MOSFET miniaturization, IEEE Electron Device Letters 1, 2 (1980)
  5. [Miura-Mattausch] M. Miura-Mattausch, H. J. Mattausch, N. D. Arora, C. Y. Yang, MOSFET modeling gets physical, IEEE Circuits and Devices Magazine 17, 29 (2001)

2D MOS Capacitor

Input files:

In this tutorial we illustrate the simulation and analysis of an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in 2D as implemented in CMOS technologies and nanodevice fabrication. The first step in simulating the MOSFET is the construction and the simulation of the corresponding MOS capacitor, i.e. the Metal-Oxide-Semiconductor device, which can act as a capacitor on its own, and is an integral part of the MOSFET. The gate contact on this capacitor is the same gate contact as of the MOSFET, and it underlies the same physics in both the MOS and the MOSFET. The 2D sketch of the MOS capacitor is illustrated in the following figure 1:

Figure 1: The geometry of the 2D MOS design, and its equivalent geometry from the output file regions.vtr (colored differently in post-processing). The blue circle indicates the position of the origin of our ($x$,$y$) coordinate system.

In this tutorial we use a p-doped bulk-Si MOS with a Schottky contact at the gate (instead of a poly-Si contact), and ohmic contact at the substrate. Therefore, the effect of poly-Si depletion at the gate is not present in either of the devices in order to produce the C-V characteristics of our capacitor, which then is the same MOS device used within the N-Ch MOSFET. The bulk p-doping level is $1 \times 10^{16} \ \ \mathrm{cm^{-3}}$, and the oxide layer which consists of SiO2 has a thickness of $d_{\rm ox} = 5 {\rm ~nm}$. The length of the channel is $L_{\rm G}=100 {\rm ~nm}$, the substrate has a height of $H_{\rm Substrate} = 200 {\rm ~nm}$. The importance of the C-V characteristics of the MOS device derives from the fact, that the charge inversion layer, that is responsible for conduction in the MOSFET, is generated by the capacitive properties of the MOS devices.

Low-Frequency Capacitance

In what follows are the results of our numerical calculations. Concretely, we solve the coupled Schrödinger, Poisson and current equations in two dimensions. We compare our results with the analytic formulas given in standard text books.

The low-frequency capacitance of a MOS capacitor can be measured experimentally with a low frequency signal. In the simple case scenario, the interface trapped charges (charges trapped in the oxide) usually play no role in the capacitance of the device and are not considered in our simulations. Therefore the total capacity of the device is a series connection of the oxide capacitance and the depletion layer capacitance,

\begin{equation} \label{eq:1} C_{\rm tot} = \frac{C_{\rm ox}C_{\rm D}}{C_{\rm ox}+C_{\rm D}}. \end{equation}

The oxide capacitance is the capacitance of the oxide layer, which is independent of the bias, and is simply calculated according to $C_{\rm ox} = \varepsilon_{\rm ox}/d_{\rm ox}$. This gives a capacitance per unit area (${\rm F}/{\rm cm}^2$). Multiplying this value with the length $L_{\rm G}$ and width $W$ of the gate gives a capacitance in units of $\rm F$.

The depletion layer capacitance is calculated using the charge in the depletion layer as defined in equation \ref{eq:2},

\begin{equation} \label{eq:2} Q_{\rm D} = qW_{\rm D}N_{\rm Sub} \ \ \ \ \ \ , \ \ \ \ W_{\rm D} = \sqrt{\frac{\varepsilon_{\rm s}^{2}}{C_{\rm ox}^{2}}+\frac{2\varepsilon_{\rm s}V}{qN_{\rm Sub}}}-\frac{\varepsilon_{\rm s}}{C_{\rm ox}}, \end{equation}

where $W_{\rm D}$ is the width of the depletion layer, $\varepsilon_{\rm s}$ is the dielectric constant of the semiconductor and $\varepsilon_{\rm ox}$ the dielectric constant of the oxide. The depletion layer capacitance is then given by the derivative $\partial Q_{\rm D}/\partial \psi_{\rm s}$, where $\psi_{\rm s}$ is the surface potential. Further details on the surface potential can be found in the appendix section. Therefore, the total capacitance calculated according to these formulas would approximately approach the $C_{\rm ox}$ at its maximum, would have a flat-band capacitance $C_{\rm FB}$ given by the expression in equation \ref{eq:3}, i.e. the capacitance at the voltage, which creates the flat-band condition in the MOS band structure,

\begin{equation} \label{eq:3} C_{\rm FB}(\psi_{\rm s}=0) = \frac{\varepsilon_{\rm s}\varepsilon_{\rm ox}}{\varepsilon_{\rm s}d_{\rm ox}+\varepsilon_{\rm ox}L_{\rm D}} \ \ \ \ \ \ \ , \ \ \ \ \ \ \ L_{\rm D} = \sqrt{\frac{k_{\rm B}T\varepsilon_{\rm s}}{q^{2}N_{\rm Sub}}}, \end{equation}

with $L_{\rm D}$ as the Debye screening length. The Debye length for our MOS capacitor amounts to $\approx 40.8 {\rm ~nm}$, and with that the flat-band capacitance is calculated to be $C_{\rm FB} \approx \ 1.85 {\rm ~mF/m^2}$, the equivalent of $ 1.85 {\rm ~pF/cm}$ if the channel length is $100 {\rm ~nm}$. The C-V curve of the MOS, taking the entire substrate for charge integration, with $\partial Q_{\rm Sub} / \partial V_{\rm Bias}$ is shown in figure 3. Note that the output of the simulations, however, is only the total charge (per cm in 2D), as shown in figure 2, which needs to be (first multiplied with the elementary charge $|q|$, and then) integrated with respect to the bias voltage:

Figure 2: The total charge carriers per cm of the MOS, integrated in the substrate, vs. the applied gate bias.
Figure 3: The C-V characteristics of the 2D MOS with $N_{\rm Sub}=10^{16} {\rm ~cm^{-3}}$ doping concentration in the p-doped silicon substrate, channel length of 100 nm, a Schottky barrier of $\phi_{\rm B} = 3.95 {\rm ~eV}$, and a charge integration region equal to the entire substrate. (Note that the flat-band voltage has been chosen from the observation of the band edges in the simulation output, which are flat for the bias value of $-0.1 {\rm ~V}$).

In the above figure the $C^{*}_{\rm FB}$ is marked with * because the value measured differs from the calculated value. Later we will show how the C-V curve could be measured, so that the value of the flat-band capacitance is consistent with $\ref{eq:3}$.

There are three values which we read from the graph (actually four but since we have the band edges here in the simulation output, we just need three). The first is the oxide capacitance $C_{\rm ox}$, which is approximately the ceiling of the curve. The second is the flat-band capacitance $C_{\rm FB}$, corresponding to the value of the flat-band voltage $V_{\rm FB}$ (read from the status of the band edges in the simulation output). And the third is the threshold voltage $V_{\rm Th}$, which is the onset of the strong inversion. The flat-band condition in the 1-dimensional band edges output is illustrated in figure 4:

Figure 4: The alignment of conduction and valence band edges with respect to the Fermi levels of the 2D MOS under the flat-band condition along a one-dimensional slice along the y direction. (The lowest conduction band edge is labeled with X.)

The bias voltage that results in a band structure in the figure 2, is called the flat-band voltage $V_{\rm FB}$. This voltage is related to, and is a part of the definition of the threshold voltage,

\begin{equation} \label{eq:4} V_{\rm Th} = V_{\rm FB}+2\psi_{\rm B}+\frac{\sqrt{4\varepsilon_{\rm Si}q N_{\rm Sub}\psi_{\rm B}}}{C_{\rm ox}}. \end{equation}

The $\psi_{\rm B}$ is the distance of the semiconductor Fermi level to the mid-point of the band gap, and it is estimated that the onset of the strong inversion is at the point when the surface potential $\psi_{\rm s} \approx 2\psi_{\rm B}$. This surface potential is estimated to be

\begin{equation} \label{eq:5} \psi_{\rm s}(\mathrm{strong \ \ inversion}) \approx \frac{2k_{\rm B}T}{q} \mathrm{ln}\left(\frac{N_{\rm Sub}}{n_i}\right). \end{equation}

Calculating this expression for our system, the surface potential amounts to $\approx 0.713 {\rm ~V}$, while the expression $ \sqrt{4\varepsilon_{\rm Si}qN_{\rm Sub}\psi_{\rm B}}/C_{\rm ox} \approx 0.073 {\rm ~V}$, which is actually the voltage drop across the oxide layer $V_{\rm ox}$. Therefore taking the flat-band voltage $V_{\rm FB} = -0.1 {\rm~V}$, we arrive at a threshold voltage $V_{\rm Th} \approx 0.7 {\rm ~V}$, which is somewhat lower than the $0.73 {\rm ~V}$ read from the curve. Indeed the value of the threshold voltage is strongly affected by the value of the Schottky barrier.

The height of the Schottky barrier used here, however, has to reflect the metal-SiO2 interface barrier, and not the metal-semiconductor barrier. This barrier depends on the metal and its work function that is used, and is therefore different for different metals. It is also mentioned in [Wu], that “the work function of the metal gate has to be properly defined in order to achieve the expected threshold voltage $V_{\rm Th}$”. Even though that the barrier heights for metals such as aluminum have been reported to be around $3.15 {\rm ~eV}$, the barrier height of metals such as gold (Au), and silver (Ag), have been reported to be around $4.0 {\rm ~eV}$ [Goetzenberger]. Here, in order to arrive at a threshold voltage of 0.7 V, the barrier had to be chosen 3.95 eV.

The Schottky Barrier, Doping Concentration, Depletion Region

in the following part we look at a set of figures, which illustrate various parameter changes, which then lead to variations in the three important values which we want to read from the C-V curve. First would be the threshold voltage, and the flatband voltage, both of which could be influenced by the height of the Schottky barrier, and the doping concentration in the bulk-semiconductor, as figure 5 illustrates :

Figure 5: The comparison of the C-V characteristics of the 2D MOS for varying Schottky barrier and the substrate doping concentration, and their effects on the threshold voltage (vertical blue lines), and the flatband voltage (vertical red lines)

As it could be seen in the above figure 5, both the barrier height and the doping concentration shift the threshold voltage $V_{\rm Th}$, and the flatband voltage $V_{\rm FB}$, however the flatband voltage is more affected by the barrier height rather than the doping concentration. It is also worth mentioning, that the doping concentration alone also affects the minimum capacitance in both low-frequency regime, and the high frequency regime, namely $C_{\rm min}$, and $C^{'}_{\rm min}$, which are the bottom limits of the C-V curve ($C^{'}_{\rm min}$ is directly inversely related to the maximum depletion region width, and apparently so is the $C_{\rm min}$).

In the next set of figures we see, how changing the charge integration region can affect the C-V curve, which then would answer why the $C^{*}_{\rm FB}$ in our original curve did not exactly match the calculated flatband capacitance $C_{\rm FB}$. The following figure 6, illustrates the effect of changing the charge integration region on the flatband capacitance $C_{\rm FB}$:

Figure 6: The comparison of the C-V characteristics of the 2D MOS for varying the width of the charge integration region.

And figure 7 shows the C-V curve of the MOS capacitor for a charge integration region of $W_{\rm int}=300 {\rm ~nm}$:

Figure 7: The comparison of the C-V characteristics of the 2D MOS for varying the width of the charge integration region.

Now it seems that the value of the flatband capacitance $C_{FB}$ in the C-V curve ($1.84 \ \mathrm{pF/cm}$) agrees very well with the calculated value. The reason for that is that, as mentioned in equation \ref{eq:2}, the charge in the depletion region is directly proportional to the width of the depletion region. This width has a maximum which is given by:

\begin{equation} \label{eq:6} W_{\rm D,max} \approx \sqrt{\frac{2\epsilon_{s}\psi_{s}({\rm strong~inv.})}{qN_{\rm A}}} \approx \sqrt{\frac{2\epsilon_{s}k_{\rm B}T\mathrm{ln}(N_{\rm A}/n_{i})}{q^{2}N_{\rm A}}} \end{equation}

which turns out to be $\approx 303 {\rm ~nm}$ in our MOS capacitor. Therefore, it should be noted, that in order to be able to reach the flatband capacitance defined by the formalism, the charge integration region should be greater or equal to the maximum depletion region width $W_{\rm D,max}$. Note that the charge carrier integration has to be specifically mentioned as a region with the following flags in the integrate{} group:

      rectangle{ # Si Charge Carrier Integration Zone
         x = [-$L_Oxide_Ch/2 , $L_Oxide_Ch/2]
         y = [-$H_Substrate, 0]
         name = "Si"
         electron_density{}         # n-charge carriers
         hole_density{}             # p-charge carriers
         label = "Si_Substrate"

The total charge is then $q(-p_{\rm tot}+n_{\rm tot})$. The derivative of this charge with respect to the voltage bias sweep results in the C-V curve, as mentioned before.

Appendix: 2D MOS

The MOS capacitor is a 2D device in its correct form for simulations (with the optional 3rd dimension if need be…). The width of the substrate needs to be somewhat larger than the channel length, so that the depletion layer charges have enough space to expand, also the boundary conditions have to be set to non-periodic in the simulation. That is because even though the channel length is set by the length of the gate-contact, and the inversion layer is bounded by the this length, this is not the case for the charges in the depletion layer. Figure 8 illustrates this phenomenon:

Figure 8: The spatial distribution of charge carriers (electrons) in the inversion layer during inversion, compared to the ones (holes) in the depletion region during depletion.

If we set the substrate width to the length of the channel, which basically would mean that the MOS could also be simulated in 1D, the C-V curve would look like the following in figure 9 :

Figure 9: The C-V curve of the quasi 1-D Simulations of the MOS (this is when we set the length of the oxide and the channel-length equal in a 2D simulation and set the boundary condition in x-direction as periodic).

As seen in the C-V curve, not only the oxide capacitance $C_{ox}$ is somewhat less than what it should be, the flatband capacitance $C_{FB}$ ($1.57 {\rm pF/cm}$) does not agree, within an acceptable margin of error, with the calculated value.

With regards to the surface potential $\psi_{s}$, it is worth mentioning, that this potential can be measured by measuring the electrostatic potential at the semiconductor-oxide interface, as function of the gate-voltage. For that in nextnano++, one needs to perform a bias sweep at the gate-contact using the template, and make a 1D-section slice of the simulation in the output{}, mentioning a range in y-direction around $y=0$, so that exactly one grid point falls within this range:

    section1D{                 # output a 1D section of the simulation area (1D slice)
      name = "surface_potential"              # name of section enters file name
      x = 0             
      range_y = [-0.2, 0.0]    # 1D slice at x = 0 through the middle of the channel 
                                              # however limited to the range in y

Using the post-processing in the template, one can then construct a curve, which should look like the one shown in figure 10:

Figure 10: The surface potential, at the semiconductor-oxide interface $\psi_{s}$, as a function of the gate.voltage $V_{G}$

Such a curve would go through the origin for an ideal MOS device, however depending on how the electrostatic potential is calculated at the contacts, this curve could go higher or lower on the y-axis. The transition from accumulation to strong inversion of the total capacitance happens basically in the region of the potential, where the line is drawn, for which $\Delta \psi_{s} \approx 2 \psi_{B}$.

The last remark regarding the capacitance of the MOS could be that, even though the classical formula of parallel plates capacitor is also here applied to the oxide capacitance, in small dimensions and in few nanometer regime, other effects such as tunneling current, and thermionic emissions could play a significant role. Additionally, since the quantum mechanical charge distribution distances itself from the semiconductor-oxide interface (as we shall see in the inversion layer comparison of the MOSFET), these effects would significantly reduce the maximum capacitance of the MOS. As we could see from the C-V curve the flatband capacitance is less than $30 \ \%$ of the oxide capacitance, even though one would expect that the $C_{FB}$ be somewhere around $80 \ \%$ of the $C_{ox}$. Therefore if the aforementioned effects be taken under consideration, it could very well be that the $C_{ox}$ fall to half of its parallel-plate value.


Input files:

The MOSFET is a transistor, which is made of a MOS capacitor in the middle and a source-drain channel for conduction. The channel of the MOSFET, which is probably the most important aspect of the MOSFET, extends from source to drain, and is created by a charge carrier inversion layer in the MOS. In this tutorial we simulate an N-channel MOSFET based on the proposed model in [Wu]. As parameters, we vary the oxide thickness, channel length and the doping profiles and investigate how these changes affect the simulation results. These quantities are defined as follows: \[ d_{\rm oxide}=t_{\rm ox} = 5 {\rm ~nm}, L_{\rm Ch}=100 {\rm ~nm}, N^{+} = 10^{20} {\rm ~cm}^{-3}, P= 10^{16} {\rm ~cm}^{-3}. \] The overall geometry of the simulated N-Ch MOSFET in this tutorial is illustrated in the following figure 11:

Figure 11: The geometry of the N-Ch MOSFET design, and its corresponding geometry from the output file user_index.vtr. The individual regions can also be found in the output file regions.vtr.

The drain-source current of the MOSFET is given by equation \ref{eq:7}:

\begin{equation} \label{eq:7} I_{\rm DS} = \frac{W}{L}\mu^{\mathrm{eff}}_{n}C_{\rm ox} \Bigg\{ (V_{\rm GS}-V_{\rm Th})V_{\rm DS} - \Bigg[ \frac{1}{2}+\frac{\sqrt{4\epsilon_{\rm Si}qN_{\rm Sub}\psi_{\rm B}}}{C_{\rm ox}} \Bigg]V_{\rm DS}^{2} \Bigg\} \end{equation} where the threshold voltage $V_{\rm Th}$ is the same threshold voltage for the MOS as defined in equation \ref{eq:4}. For the limit of $V_{\rm DS} \ll (V_{\rm GS} - V_{\rm Th})$ equation \ref{eq:7} reduces to: \begin{equation} \label{eq:8} I_{\rm DS} = \frac{W}{L}\mu^{\mathrm{eff}}_{n}C_{\rm ox} (V_{\rm GS}-V_{\rm Th}-\frac{V_{\rm DS}}{2})V_{\rm DS} \end{equation} For the input characteristics, this equation becomes a function of the gate voltage $V_{\rm GS}$ with the drain-source voltage $V_{\rm DS}$ kept constant. For the output characteristics, however, this current becomes a function of the drain-source voltage at constant gate voltage. (But rather for a set of gate voltages.) As can be seen the current is directly proportional to the effective mobility $\mu^{\mathrm{eff}}$, and the oxide capacitance of the MOS capacitor $C_{\rm ox}$. Note that $C_{\rm ox}$ is the oxide capacitance per unit area in 3D (and per channel length in 2D), and therefore has the units of $ F/(\mathrm{length})^{2} $.

Input Characteristics

Using the Masetti mobility model, we have calculated the input characteristics of the MOSFET classically, which is shown in figure 12 on a linear scale,

Figure 12: The input characteristics of the N-Ch MOSFET calculated classically with Masetti mobility, showing the position of the threshold voltage $V_{Th}$.

and in figure 13, on a logarithmic scale:

Figure 13: The input characteristics of the N-Ch MOSFET calculated classically with Masetti mobility, showing the drift and diffusion current regions on the logarithmic scale.

The above input characteristics were calculated without the shift in the drain contact. This could modify the results in a certain way that is worth noting. More on this could be found in the Appendix: MOSFET. According to [ref3], the extrapolation of the linear region meets the x-axis at $V_{\rm Th} + \frac{V_{\rm D}}{2}$. Having set the $V_{\rm DS}$, to $0.2 {\rm ~V}$, for the calculation of the input characteristics, the value is very well expected to be $\approx 0.8 {\rm ~V}$, since the threshold voltage $V_{\rm Th}$ was calculated to be $\approx 0.7 {\rm ~V}$. However we also used a small backgate bias $V_{\rm BS}=-0.1 {\rm ~V}$ in the above calculations, which slightly modifies the threshold voltage, by changing the voltage drop in the oxide to, \[ V_{\rm ox} = \frac{\sqrt{2\varepsilon_{\rm Si}qN_{\rm Sub}(2\psi_{\rm B}-V_{\rm BS})}}{C_{\rm ox}} \approx 0.08 {\rm ~V}, \] compared to $V_{\rm ox} = 0.073 {\rm ~V}$. However the difference is negligible in our case. Note that the above input characteristics were calculated without a shift in the drain contact. This can also modify the results to a certain degree as explained in the Appendix section.

However the input characteristics could also be calculated quantum mechanically, since we only have to define the inversion layer region as a quantum region. The prediction is that the charge carrier inversion layer would shift slightly away from the oxide, since the wavefunction amplitude would have to fall to zero at the oxide-semiconductor interface. This phenomenon is illustrated in figure 14:

Figure 14: The comparison of the charge inversion layer of the N-Ch MOSFET calculated classically (right), and quantum mechanically (left) (at $V_{\rm GS} \gt V_{\rm Th}$ and $V_{\rm DS}=0.2 {\rm ~V}$).

The following set of curves in figure 15 are the comparison of the input characteristics calculated classically and quantum mechanically:

Figure 15: The comparison of the input characteristics of the MOSFET calculated classically and quantum mechanically.

As the simulations show there is a slight difference in the input characteristics, most importantly the leakage current, which is the current below the threshold voltage, which turns out to be less for the quantum mechanical input characteristics.

Output Characteristics

The output characteristics of the MOSFET is the I-V characteristics of the drain current $I_{\rm DS}$ vs. the source drain voltage $V_{\rm DS}$, for certain constant gate voltage. Therefore the output characteristics could be viewed as a double sweep, and considering the total simulation time, it is a heavy load on the simulator. With that in mind its worth mentioning that the issue of convergence becomes very important for the output characteristics, in the sense that if the simulation parameters are not chosen correctly the simulations may never converge. More on that could be found in the Appendix: MOSFET. The output characteristics of the MOSFET calculated with the Masetti mobility are shown in figure 16:

Figure 16: The output characteristics of the N-Ch MOSFET calculated classically with Masetti mobility, showing the linear and the saturation regions of the output characteristics.

The slope of the black line which covers the linear region of all the curves, can be used to calculate the channel specific resistivity. Now if we take the width of the MOSFET to be $15 {\rm ~nm}$, as it was the case for the model in [ref], the output characteristics could be expressed in Amperes, as shown in figure 17:

Figure 17: The output characteristics of the N-Ch MOSFET calculated classically with Masetti mobility, showing the linear and the saturation regions of the output characteristics for a width of $15 {\rm ~nm}$.

From the readings on the curve we can estimate the specific channel resistivity, \[ \frac{1}{R_{\rm specific}} = \frac{L}{W}\frac{I_{\rm DS}}{V_{\rm DS}} \rightarrow R_{\rm specific} = 1.8 {\rm ~k} \Omega. \] As mentioned before, the output characteristics can be divided into two regions, the ohmic region and the saturation region. The transition to the saturation region happen at the $V_{\rm DS,sat}$, which is give by equation \ref{eq:9}:

\begin{equation} \label{eq:9} V_{\rm DS,sat} = \frac{V_{\rm GS} - V_{\rm Th}}{M} \ \ \ , \ \ \ M = 1 + \frac{K}{2\sqrt{\psi_{\rm B}}} \ \ \ \ , \ \ \ \ K = \sqrt{\varepsilon_{s}qN_{\rm A}}/C_{\rm ox} \end{equation} This value obviously is meaningful for $V_{\rm GS} > V_{\rm Th}$, as it is zero for $V_{\rm GS} = V_{\rm Th}$, and the $M$ factor is a dimensionless factor equal to $\approx 1.051$ for our system. The saturation current is then defined as the current that is measured at $V_{\rm DS,sat}$, for each $V_{\rm GS}$ as defined in equation \ref{eq:10}: \begin{equation} \label{eq:10} I_{\rm DS,sat} = \frac{W}{2ML}\mu^{\mathrm{eff}}_{n}C_{\rm ox}(V_{\rm GS}-V_{\rm Th})^2 = \frac{WM}{2L}\mu^{\mathrm{eff}}_{n}C_{\rm ox}V^2_{\rm DS,sat} \end{equation} and plotting this current over the output characteristics, the curve crosses each $I_{\rm DS}$, exactly at the corresponding $V_{\rm DS,sat}$ for that output current, as shown in figure 18:

Figure 18: The output characteristics of the N-Ch MOSFET calculated classically with Masetti mobility for a width of $15 {\rm ~nm}$, and the saturation current $I_{\rm DS,sat}$ plot.

If we take the effective mobility to be field-independent (which is the case in our simulations), the above $I_{\rm DS,sat}$ curve could be fitted with $I_{\rm DS,sat} = A \cdot V_{\rm DS,sat}^2$ formula, where $A$ is estimated at $A \approx 2.475 \cdot 10^{-5}$. Note that, the quadratic curve does not meet the output current curves at the points, where they are supposed to meet (at $V^2_{\rm DS,sat}$ voltages), because, as we can see, the output charateristic curves do not really saturate after drain source voltage reaches $ V_{\rm DS,sat}$. This is due to a short channel effect called drain-induced barrier lowering (or punch-through), which we will talk about in last section. When this effect diminishes (as we shall see), the quadratic curve meets the output-curves exactly at the saturation voltage point $ V_{\rm DS,sat}$.

From the fit parameter estimate, and the rest of the known parameters, we can however estimated the effective mobility $\mu^{\mathrm{eff}}_{n}$ independent of the field for the short channel case in an approximate way (and compared it later on with the long-channel variant). Taking the oxide capacitance to be $C_{\rm ox} \approx 6.6 {\rm ~mF}/{\rm m}^2$, the effective mobility of the electrons is then estimated to be \[ \mu^{\mathrm{eff}}_{n} \approx 525 \ \frac{\mathrm{cm}^2}{\mathrm{V \cdot s}}, \] The calculated bulk mobility from the simulations is given to be $\approx 933 \ \mathrm{cm}^2/\mathrm{Vs}$ in the p-doped substrate, and $\approx 567 \ \mathrm{cm}^2/\mathrm{Vs}$ at $y=0$, which is the semiconductor-oxide interface.

Transconductance and Channel Conductance

In many cases, a MOSFET is used for signal amplification, as opposed to switching function, which is the case in CMOS, and digital logic circuits. For this purpose quantities such as transconductance and channel-conductance become important. The transconductance is defined as the derivative of the output current $I_{\rm DS}$ with respect to the gate voltage $V_{\rm GS}$, for a constant source-drain voltage $V_{\rm DS}$: \begin{equation} g_{m} = \frac{\partial I_{\rm DS}}{\partial V_{\rm GS}} \biggr\rvert_{V_{\rm DS} = {\rm const.}} \end{equation} Figure 19 shows the tranconductance curve and its maximum value:

Figure 19: The transconductance of the MOSFET as a a derivative of the source-drain current $I_{\rm DS}$ with respect to the gate voltage $V_{\rm GS}$.

The maximum value of the transconductance read from the curve amounts to $\approx 7.7 \ \mathrm{A/Vcm}$. However, it could also be calculated manually using the equation \ref{eq:12}, since we now know the value of the effective mobility:

\begin{equation} \label{eq:12} g_{m} = \frac{\partial I_{\rm DS}}{\partial V_{\rm GS}} \biggr\rvert_{V_{\rm DS} = {\rm const.}} = \frac{W}{L}\mu^{\mathrm{eff}}_{n}C_{\rm ox}V_{\rm DS} \end{equation} which amounts to $\approx 7.9 \ \mathrm{A/Vcm}$ for an eliminated $W$ ($W=1$). In contrast we have the channel conductance, which is the derivative of the source-drain current $I_{\rm DS}$ with respect to the source drain voltage $V_{\rm DS}$, at a constant gate voltage $V_{\rm GS}$,as defined in equation \ref{eq:13}: \begin{equation} \label{eq:13} g_{\rm D} = \frac{\partial I_{\rm DS}}{\partial V_{\rm DS}} \biggr\rvert_{V_{\rm GS} = {\rm const.}} = \frac{W}{L}\mu^{\mathrm{eff}}_{n}C_{\rm ox}(V_{\rm GS}-V_{\rm Th}) \end{equation} which is in turn a function of the gate voltage $V_{\rm GS}$. Figure 20 illustrates this conductance for a set of gate voltages:

Figure 20: The channel conductance of the MOSFET as a derivative of the source-drain current $I_{DS}$ with respect to the source-drain voltage $V_{\rm DS}$.

Note that all of the curves in the above figure are from the same family. they are only stretched and displaced with respect to each other since the arguement $(V_{\rm GS} - V_{\rm Th})$ acts as a displacement and multiplication factor for the curves for each $V_{\rm GS}$.

Finally we have for the $V_{\rm DS} \geq V_{\rm DS,sat}$, the saturation transconductance which is derivative of the quadratic current output equation $I_{\rm DS}$ in \ref{eq:14} with respect to $V_{\rm GS}$: \begin{equation} \label{eq:14} g_{m} = \frac{\partial I_{\rm DS}}{\partial V_{\rm GS}} \biggr\rvert_{V_{\rm DS} \geq V_{\rm DS,sat}} = \frac{W}{ML}\mu^{\mathrm{eff}}_{n}C_{\rm ox} (V_{\rm GS}-V_{\rm Th}) \end{equation} which would be straight line with respect to $V_{\rm DS}$, and $V_{\rm GS}$.

Comparison of Different Mobility Models

The effect of the correct mobility model for the simulations of such devices as MOSFETs cannot be overstated. It is an established fact, that the best mobility models used for simulating the current transport in the channel are those that are field dependent, and therefore are modified along the channel as a result of the perpendicular (and also parallel) field. The simplest of these models is the velocity saturation model which sets a maximum value for the drift velocity as the function of the field, and with that the mobility is limited by the maximum velocity. There are of course also more complicated models such as the enhanced Lombardi model, or inversion layer mobility models, which also take into account the scattering of the charge carriers at the semiconductor-oxide interface. These are very specialized models, specifically designed for the simulation of such devices as MOSFETs, and other field effect devices, and are implemented in specialized commercial TCAD tools used by industry. Here we are limited to the already implemented mobility models, which hopefully in the near future will expand. These are the Masetti model, Arora model, Minimos model, and constant mobility model. Figure 21 illustrates the effect of different mobility models on the input characteristics of the MOSFET:

Figure 21: The input characteristics of the MOSFET calculated classically with different mobility models, in normal and logarithmic scales. For the constant mobility model, the mobility for the electrons and holes was set to $\mu_{\rm n} = 460 {\rm ~cm^2/Vs}$ and $\mu_{\rm p} = 160 {\rm ~cm^2/Vs}$, respectively.

In the above curves, interestingly enough the Masetti model seems to reach the saturation much sooner than the other ones, and the constant mobility model seems to be a straight line, even though the value of the constant mobility is much lower in the inversion layer than the rest of the mobility models ($460 \ \mathrm{cm^2/Vs}$ compared to $900-1000 \ \mathrm{cm^{2}/Vs}$). The reason for that is that the constant mobility model defines the same electron mobility in the inversion layer, which is a p-doped region, as well as in the source and drain contact regions, which are heavily n-doped regions, whereas the other doping dependent mobility models have significantly different values for these regions, and the fact is that, in order for the current to flow, it must reach the contacts, which are the heavily n-doped regions. That is why the constant mobility produces a different input characteristics curve than the other mobility models. Also regarding the Masetti model, the reason that this model reaches the saturation faster could be attributed to the ratio of the mobility in the p-doped region with respect to the n-doped region, which for the Masetti model is $\approx 12$, while it is $\approx 10$ for the Minimos and Arora models. Obviously, this ratio is 1 for the constant mobility model.

The following figure 22 shows the output characteristics calculated with the constant mobility model set at $\mu_{0} \approx 460 \ \mathrm{cm^2/Vs}$:

Figure 22: The output characteristics of the MOSFET calculated classically with the constant mobility model, taking the width $W$ to be $ 15 {\rm ~nm}$.

We can now compare this to the Masetti mobility as the example of doping dependent models. Figure 23 shows the comparison for a selection of the $V_{\rm GS}$ values:

Figure 23: The comparison of the output characteristics of the MOSFET calculated classically with constant mobility and Masetti models, for a selection of gate voltages, and the width $W = 15 {\rm ~nm}$.

As the curves suggest, the difference is negligible for very high and very low gate voltages. The difference becomes significant only for $ 1.5 \leq V_{\rm GS} \leq 2.5 \ \mathrm{V}$.

Furthermore, it is worth mentioning, that a good mobility model for the inversion layer in the MOSFET should have two field dependencies, one being the perpendicular field originating from the gate, and the other one the parallel field coming from the source-drain bias. The velocity saturation method, which has recently been implemented would only have one of these components, namely the parallel field dependency, and since it is still at the experimental level, we did not put any results simulated with that. However the implementing velocity saturation would have a distinguishable effect on the output characteristics of the short channel MOSFET.

Channel Length Modulation and Pinch-Off Effect

One last effect that is worth talking about in the context of the output characteristics, is the pinch-off effect, i.e. the effective shortening of the channel length, which is known as the channel length modulation. It is said that the pinch-off effect steps in at the onset of saturation $V_{\rm DS} \approx V_{\rm DS,sat}$. Figure 24 shows the electron density along the channel for 3 different source-drain voltages ($V_{\rm DS} = 0.0 {\rm ~V}$, $V_{\rm DS} = 0.6 {\rm ~V}$, $V_{\rm DS} = 1.5 {\rm ~V}$) at a fixed gate voltage $V_{\rm GS} = 2.0 {\rm ~V}$:

Figure 24: The comparison of the electron density distribution in the channel for $V_{\rm DS}=[0.0, 0.6, 1.5] {\rm ~V}$ at the gate voltage of $V_{\rm GS} = 2.0 {\rm ~V}$, showing the pinch-off effect and the effective channel shortening. The 3 pictures of the left show the electron density n(x,y) which is contained in the file density_electron.vtr. The 3 pictures of the right show the content of the file density_electron_1d_middle_line_x_direction.dat which contains a slice along the x direction for constant y value where y lies in the channel for the pictures on the left.

Then the saturation current equation takes the following form: \begin{equation} I_{\rm DS,sat} = \frac{W}{2ML}\mu^{\mathrm{eff}}_{n}C_{\rm ox}V^2_{\rm DS,sat}(1+\lambda V_{DS}) \end{equation} with $\lambda \approx \Delta L /L \cdot V_{\rm DS}$. However this is not an analytical approach, and can possibly lead to inconsistencies. There is a more precise way to calculate the effective channel length, if we take into consideration the depletion widths of the source and drain under potential difference. Figure 25 illustrates these depletion widths:

Figure 25: The illustration of the shortening of the effective channel length due to the expansion of the drain and source depletion widths.

Using the built-in potential of the pn junction at the source and drain $\psi_{\rm bi} \approx 0.9 {\rm ~V}$, and the surface potential $\psi_{\rm s} = 2\psi_{\rm B} \approx 0.713 {\rm ~V}$, we can estimate the length of the effective channel, taking the depletion widths to be approximately equal to $y_{\rm S}$ and $y_{\rm D}$ for source and drain, within the inversion layer (meaning that the widths also include the surface potential at the semiconductor-oxide interface), as defined in equation \ref{eq:16}, \begin{equation} \label{eq:16} y_{\rm S} \approx \sqrt{\frac{2\varepsilon_{\rm s}}{qN_{\rm A}}(\psi_{\rm bi} - \psi_{\rm s} - V_{\rm BS})} \ \ \ , \ \ \ y_{\rm D} \approx \sqrt{\frac{2\varepsilon_{\rm s}}{qN_{\rm A}}(\psi_{\rm bi} + V_{\rm D} - \psi_{\rm s} - V_{\rm BS})}. \end{equation} From which then results the effective channel length (as also illustrated in figure 25), as follows: \begin{equation} L_{\rm eff} = L^{'} = L - y_{\rm S} - y_{\rm D} \end{equation} However, this analysis has an indirect implication with regards to the channel length. Namely, for given source and drain depletion regions there is a minimum channel length. And indeed there is such a consideration, which is said to separate the long channel scenario from the short channel one, meaning a channel above this minimum length is considered a long channel (and not a short channel), and the above considerations apply only to long channel MOSFETs. As we will later see there are also other effects and considerations which will apply to the case of short channels (together known as the short channel effects). The minimum channel length for the long channel case is then given by the following empirical formula in \ref{eq:17}, \begin{equation} \label{eq:17} L_{\rm min} = C \Big[r_j d_{\rm ox} (W_{\rm S} + W_{\rm D})^2 \Big]^{1/3}, \end{equation} where $C$ is a constant, and $W_{\rm S}$ and $W_{\rm D}$ are the depletion widths of source and drain, \begin{equation} \label{eq:18} W_S = \sqrt{\frac{2\epsilon_s}{qN_A}(\psi_{\rm bi} - V_{\rm BS})} \ \ \ , \ \ \ W_{\rm D} = \sqrt{\frac{2\varepsilon_{\rm s}}{qN_{\rm A}}(\psi_{\rm bi} + V_{\rm D} - V_{\rm BS})}. \end{equation} If we take $V_{\rm D} = 0.2 {\rm ~V}$, then we have $W_{\rm S} = 359 {\rm ~nm}$, and $W_{\rm D} = 393 {\rm ~nm}$, while for the same $V_{\rm D} = 0.2 {\rm ~V}$, the $y_{\rm S} = 192 \ \rm nm$, $y_{\rm D} = 198 \ \rm nm$. It makes sense to claim, that a negative effective channel length makes no sense, therefore $L_{\rm min} \geq y_{\rm S} + y_{\rm D}$. In [Brews] it is mentioned, that the constant $C$ for device parameters of: $d_{\rm ox} = 25 \ \rm nm, r_j = 330 \ \rm nm, N_{\rm A} = 10^{14} \ \rm cm^{-3}, V_{\rm DS} = 1 \ \rm V, V_{\rm BS} = \ \rm 0$, through single point fitting, was measured to be $0.41 \ \rm A^{1/3}$. For this value of the constant, our $L_{\rm min}$ would have to be $198 \ \rm nm$, which is almost half the value of $y_{\rm S} + y_{\rm D}$. However, for a value of $C = 0.8 \ \rm A^{1/3}$, we would have a $L_{\rm min} = 390 \ \rm nm$. Though if we take the fact, that we increase our drain source voltage all the way to $V_{\rm DS} = 2.0 \ \rm V$, then $y_{\rm D}$ would go as high as $540 \ \rm nm$. Then it would be safe to claim, that we need our channel to be at least $\approx 600 \ \rm nm$. Now let us examine the consistency of the $y_{\rm S}$, and $y_{\rm D}$ values, for a channel length of $L = 2000 \ \rm nm$. The following figure 26 illustrates the pinch-off effect and channel length modulation in the same MOSFET model with a $L_{\rm G} = 2 \ \rm \mu m$:

Figure 26: The illustration of the pinch-off effect, and the channel length modulation, in the N-Ch MOSFET with a channel length of $L_{\rm G} = 2 \ \rm \mu m$, calculated classically. The depletion widths at the source and drain, $y_{\rm S}$ and $y_{\rm D}$, estimated from the analytical formulas given above, are indicated.

So therefore, according to the calculations in figure 26, the effective channel length should be $L_{\rm eff} \approx 1330 \ \rm nm$. Furthermore, it seems that the effects at the boundaries are not compatible with the calculations. However, the shortening of the boundaries due to the applied voltage at the drain is somehow in line with the depletion length $y_{\rm D}$.

Short Channel Effects, DIBL and Punch-Through

So as we established in the previous section, our MOSFET, with a $100 \ \rm nm$ channel, length would be below the long channel limit, and therefore would experience short channel effects. The most important of these effects is known as the drain induced barrier lowering (DIBL), which causes the injection of extra charge carriers, resulting in the increasing of the output current even after the saturation $I_{\rm DS,sat}(V_{\rm DS,sat})$. This phenomenon is known as the punch-trough effect and is present in our output characteristics in figures 16 and 17 of the output characteristics section. The DIBL effect is shown in figure 27, comparing two channel lengths:

Figure 27: The illustration of the drain induced barrier lowering (DIBL) in $100 \ \rm nm$ gate-length MOSFET, compared to the $2000 \ \rm nm$ gate-length variant (where there are no barrier lowering).

In order to recognize the punch-through effect, the sweep of the gate-length should be performed at high drain-source voltages (for example $V_{\rm DS} = 2.0 \ \rm V$ $) with the input characteristics on a logarithmic scale, whihc then show if the drift current is limited due to the gate length of the MOSFET. Figure 28 shows this effect:

Figure 28: The punch-through effect for a set of channel lengths in MOSFET apparent in the input characteristics (calculated with minimum density of $\rm 10e4$).

As it could be seen in 28, the MOSFET with gate-length of $L_G \leq 400 \ \rm nm$ would definitely suffer from the punch-through effect. However, one could be safe with a channel length of $500 \ \rm nm$ or $600 \ \rm nm$. Let us now examine the effect of channel length on the normal input characteristics, namely at low drain source voltage. Using the Masetti mobility, the effect of increasing the channel length is illustrated in figure 29:

Figure 29: The effect of increasing the channel length on the input characteristics at $V_{\ \rm DS}=0.2 \ \rm V$.

So therefore we expect, that our input characteristics will be the same for a channel length of $400 \ \rm nm$ or above using any of the mobilities (Masetti, or constant, or any other), as long as there is no field-dependent saturation in the mobility model. In the following 30 let us estimate the threshold voltage for an ideally long channel MOSFET variant ($L_{\rm G} = 600 \ \rm nm$):

Figure 30: The input characteristics of the long-channel $L_{\rm G} = 600 \ \rm nm$ MOSFET, calculated with the Masetti mobility, showing the value of the threshold voltage $V_{\ \rm Th}$.

From which it could be concluded, that the threshold voltage is $V_{\rm Th} \approx 0.87 \ \rm V$. Consequently the output characteristics for the $L_{\rm G} = 600 \ \rm nm$ MOSFET is shown in figure 31:

Figure 31: The output characteristics of the long-channel $L_{\rm G} = 600 \ \rm nm$ MOSFET, showing the diminishing of DIBL effect.

As we can see in the above figure, the quadratic curve fits the output current curves exactly at the proper voltage point, which is $V_{\rm DS,sat}$. The fit factor for this MOSFET variant is $\approx 6.19 \times 10^{-6}$. Using this fitting factor, and taking into consideration the new channel length $L_{G} = 600 \ \rm nm$, we get for the effective mobility: \[ \mu^{\mathrm{eff}}_{n} \approx 788 \ \rm \frac{cm^2}{V \cdot s} \] The calculated mobility from the simulation is once again $933 \ \rm cm^2/Vs$ in the substrate, however it is $576 \ \rm cm^2/Vs$ at $y=0$ coordinate.

Appendix: MOSFET

In the last section we found out, from the comparison of the input characteristics at high drain-source voltage $V_{\rm DS} = 2 \ \rm V$, that the MOSFET device with a gate length of smaller than $L \leq 400 \ \rm nm$, would suffer from the punch-through effect. However, if we further shorten our gate length below $100 \ \rm nm$, the situation would even be worse. Namely the leakage current would be so high, that even at very low source-drain voltages $V_{\rm DS} = 0.2 \ \rm V$, the MOSFET would conduct, even at gate-voltages below the threshold voltage $V_{\rm GS} < V_{\rm Th}$, and therefore the switching capability of the MOSFET would be diminished and eliminated. Figure 32 illustrates this phenomenon:

Figure 32: The comparison of input characteristics of the N-Ch MOSFET calculated quantum mechanically with the Masetti mobility, showing the leakage current in the input characteristics.

As the above input characteristics cures show, for gate-length below $100 \ \rm nm$ there is basically no valid switching function possible, as the drift current has already started at $V_{\rm GS} = 0 \ \rm V$ for $L_G = 75 \ \rm nm$. This is basically to say that, at higher drain-source voltages the leakage curremt is actually more dominant to the channel inversion layer current, which can be switched on and off. It is also worth noting that the leakage current takes place inside the bulk of the MOSFET at the bottom of source drain doped region as figure 33 shows:

Figure 33: The norm of the leakage current in $L_G = 75 \ \rm nm$ MOSFET, at zero gate-voltage $V_{GS}=0$, flowing within the bulk.

If we even consider the $L_G = 25 \ \rm nm$ MOSFET, there are certain quantum mechanical affects could be observed. Using the energy_resolved_density{}, one could observe spacial confinement within the channel at different energy levels. The code has to include the following lines:

      min =  -0.5
      max =  1.0
      energy_resolution = 0.001
      only_quantum_regions = yes

      min =  -0.5
      max =  1.0
      energy_resolution = 0.001
      only_quantum_regions = yes


But to be able to see the quantum mechanical effects, lets us first take a look at the classical energy resolved densities in the channel and the source-drain doping regions (for that the only_quantum_regions flag has to be set to no in the energy_resolved_density group). The classical energy resolved densities are shown in figure 34:

Figure 34: The classical energy resolved density in the $L_{\rm G} = 25 \ \rm nm$ MOSFET at three different energy levels.

Now let us look at the same energy resolved densities in the MOSFET source and drain region, obtained using the quantum mechanics alone:

Figure 35: The quantum mechanical energy resolved density in the MOSFET source and drain regions, showing spacial quantum confinement at discrete energy levels.

In the above figure we can clearly see that compared to the classical density, the quantum mechanical density indicate quantum confinement in the source drain doping regions. Furthermore, as we shall see in figure 36, also the density in the inversion layer shows quantum confinement for different discrete energy levels:

Figure 36: The quantum mechanical energy resolved density in the inversion layer of the MOSFET-channel, at two different energy levels, showing the standing wave pattern, which indicates quantum confinement.

As we can see there is clearly two different quantum confined modes in the inversion layer of the channel for this MOSFET.

With regards to the issue of convergence for the output characteristics, the convergence parameters become very relevant, since for the wrong set of parameters, the simulations may very well never converge and if so might take a significant amount of time. The key parameter to keep in mind is the alpha_fermi parameter in current-poisson{} calculations, which would decide the fate of the calculations. This parameter needs to be chosen corrently, and also since it will be dynamically reduced, the alpha_scale parameter also need to be set appropriately, with a relatively small alpha_iterations (default is 1000, which is very high!!!), so that a quick adjustment can be achieved if the parameter is too large. One also needs to significantly increase the number of iterations from the default 100, to a few thousand. This so called under-relaxation parameter for the quasi-Fermi level is important due to the fact that it decides the volume of the search for the solutions. If the solution somehow is located outside of this volume

nnp/mosfet_in_2d.txt · Last modified: 2020/08/03 15:01 by daryoush.nosraty-alamdary